1. Field of the Invention
The present invention relates to an output buffer circuit that can correspond to a plurality of interfaces. Particularly, the present invention relates to an output buffer circuit that is used in a memory integrated circuit device and the like.
2. Description of the Background Art
A TTL (Transistor-Transistor Logic) is mainly used as the interface standard for a semiconductor integrated circuit device employed as a memory. The TTL level is determined so that an input and output of at least 2.4 V correspond to logic "1", whereas an input of not more than 0.8 V and an output of not more than 0.4 V correspond to logic "0". However, in accordance with voltage reduction of the power source used in a semiconductor device (for example, 5.0V.fwdarw.3.3 V), a LVTTL (Low Voltage TTL) which is a voltage reduced version of TTL is also used. In a LVTTL, the signal level definition is divided into a determination level (AC specification) and a final level (DC specification) to which the signal arrives. It is determined that an input and output of at least 2.0 V correspond to logic "1" and an input and output not more than 0.8 V correspond to logic "0" in the AC specification. According to the DC specification, it is determined that an input and output of at least 2.4 V correspond to logic "1", and an input of not more than 0.8 V and an output of not more than 0.4 V correspond to logic "0".
A conventional output buffer circuit for a TTL and a LVTTL interface will be described hereinafter with reference to the drawings FIG. 10 is a circuit diagram showing a structure of a conventional TLL and LVTTL interface output buffer circuit.
Referring to FIG. 10, an output buffer circuit includes n channel MOS transistors Q51 and Q52 which are connected in series. Transistor Q51 has one end connected to an output power supply voltage V.sub.cc Q. An input signal .phi.1 is applied to the gate of transistor Q51. Transistor Q52 has one end connected to an output ground voltage V.sub.ss Q. An input signal .phi.2 is applied to the gate of transistor Q52. An output signal DQ is provided from the node of transistors Q51 and Q52.
The operation of an output buffer circuit of the above structure will be described hereinafter with reference to the timing chart of FIG. 11.
When input signals .phi.1 and .phi.2 attain the level of output ground voltage v.sub.ss Q, transistors Q51 and Q52 are turned off, whereby output signal DQ attains a high resistance state (high impedance state). When input signal .phi.1 attains the level of output power supply voltage v.sub.cc Q and input signal .phi.2 attains the level of output ground voltage v.sub.ss Q, transistor Q51 is turned on and transistor Q52 is turned off. As a result, output signal DQ attains a level of (V.sub.cc Q-Vth), indicating logic "1". Here, Vth is the threshold voltage of transistor Q51. When input signal .phi.1 attains the level of output ground voltage V.sub.ss Q and input signal .phi.2 attains the level of output power supply voltage v.sub.cc Q, transistor Q51 is turned off and transistor Q52 is turned on. As a result, output signal DQ attains a level of output ground voltage v.sub.ss Q, indicating the state of logic "0". According to the above-described operation, output signal DQ is output in one of the three states according to the levels of input signals .phi.1 and .phi.2.
The need arises for increase of the operating speed of peripheral circuitry in accordance with increase in the operating frequency of recent microprocessors. Therefore, the operating speed of the above-described output buffer circuit for TTL/LVTTL interface is approaching the limit thereof. For example, there is a problem that the delay time in charging/discharging the load capacitance of approximately 100 pF to 2.4 V/0.4 V exceeds the required access time. There is also a problem that the output waveform is distorted due to overshooting, undershooting, ringing, and the like of the output signal caused by high speed switching, resulting in erroneous determination of the level. Therefore, a GTL (Gunnig Transceiver Logic) which is a high speed interface having a signal amplitude of not more than 1 V is recently used for an output buffer circuit. Such a GTL interface output buffer circuit will be described hereinafter. FIG. 12 is a circuit diagram showing a structure of a conventional GTL interface output buffer circuit.
Referring to FIG. 12, an output buffer circuit includes an open-drain n channel MOS transistor Q53. An input signal .phi.3 is applied to the gate of transistor Q53. Transistor Q53 has one end connected to output ground voltage V.sub.ss Q. Output signal DQ is provided from the drain of transistor Q53.
When input signal .phi.3 attains an H level (logical high), transistor Q53 is turned on. As a result, output signal DQ of the level of output ground voltage V.sub.ss Q is provided, indicating the state of logic "0". When input signal .phi.3 attains an L level (logical low), transistor Q53 is turned off, whereby output signal DQ attains a high impedance state.
A system employing the above-described output buffer circuit will be described hereinafter. FIG. 13 shows a structure of a system employing the output buffer circuit of FIG. 12.
Referring to FIG. 13, the system employing an output buffer circuit includes resistors R51, R52, n channel MOS transistors Q54-Q56, differential amplifiers C51-C53, and logic circuits 51-53. In FIG. 13, three logic circuits 51-53 are connected to the wiring terminated at a voltage VTT of 1.2 V via a resistor of 50.OMEGA.. The open-drain n channel MOS transistors Q54-Q56 serve as drivers, and differential amplifiers C51-C53 serve as receivers. Reference voltage VREF of 0.8 V is applied to one input terminal of each of differential amplifiers C51-C53. The drive current of transistors Q54-Q56 is approximately -40 mA.
When an output signal of logic "1"is provided from logic circuits 51-53, transistors Q54-Q56 are turned on. Here, a signal amplitude of less than 1 V is obtained due to a voltage drop caused by the drive current of transistors Q54-Q56 flowing to terminal resistors R51 and R52. When an output signal of logic "0"is provided from logic circuits 51-53, transistors Q54-Q56 are turned off. Therefore, the output signal attains the level of voltage VTT. Differential amplifiers C51-C53 compare-amplify the small voltage of the input signal with reference voltage VREF to apply the amplified signal to logic circuits 51-53.
According to the above-described GTL definition, the output level takes a value of not more than 0.4 V for logic "0"and a value of VTT=1.2 V for logic "1". In contrast, the input level takes a value of not more than VREF-50 (mV)=0.75 (V) for logic "0", and a value of at least VREF+50 (mV)=0.85 V for logic "1".
The advantage of the above-described GTL interface is set forth in the following. The impedance of the wiring, the terminal resistor, and the driver transistor is defined at the same level. Therefore, reflection of an output signal does not easily occur. Furthermore, the charge/discharge current does not increase in comparison with that of a TTL interface even when the load capacitor of the wiring is great since the signal amplitude is small.
The selection of a LVTTL or a GTL for the interface depends on, not only from the device side, but also on the target performance and the cost of the system employing a DRAM (Dynamic Random Access Memory). Particularly, the system may include a plurality of interfaces during its transition from a LVTTL to a GTL interface. Therefore, the device used in the system must include an output buffer circuit corresponding to the plurality of interfaces. This means that two types of output buffer circuits shown in FIGS. 10 and 12 must be provided within the device to correspond to both the LVTTL and the GTL interfaces.
When two types of output buffer circuits are to be provided as in the above-described case, the pull down ability of the transistor used in the GTL must be set greater than the pull down ability of the transistor of the LVTTL since the drive current of the GTL is defined at the level of 40 mA. For example, the gate width of transistors Q51 and Q52 used in the LVTTL must be 400 .mu.m, and the gate width of transistor Q53 used in the GTL must be 800.mu.m. Thus, there was the problem that the chip area is significantly increased when two types of output buffer circuits are internally provided with respective transistors used for a LVTTL and a GTL.